1. Field of the Invention
This invention relates generally to the manufacture of semiconductor devices, and more particularly to a method for encapsulating a metal via in a damascene process.
2. Description of the Related Art
Since the introduction of semiconductor devices, the size of semiconductor devices have been continuously shrinking, resulting in smaller semiconductor chip size and increased device density on the chip. One of the limiting factors in the continuing evolution toward the smaller device size and higher density has been the interconnect area needed to route interconnect lines between devices. As a way to overcome such a limitation, multilevel interconnection systems have been implemented using shared interconnect lines between two or more levels.
Originally, conventional process techniques implemented multilevel interconnection systems by depositing a metal layer, photomasking the deposited metal layer, and then etching the metal layer to form desired interconnections. However, since metals are typically more difficult to pattern and etch than other semiconductor layers such as dielectric or oxide layers, a dual damascene process has been implemented to form metal vias and interconnects by dispensing entirely with the metal etching process. Dual damascene process is a well known semiconductor fabrication method for forming metallization vias and interconnect lines.
In the dual damascene process, a via and a trench is etched in an oxide layer such as intermetal dielectric layer. The dielectric layer is typically formed over a metal layer. The via and the trench are then filled with a metal (e.g., Al, Cu) in the vias and trenches to form the metallization vias and interconnect lines, respectively. The excess metal above the trench level is then removed by well known chemical-mechanical polishing (CMP) processes.
Dual damascene process is gaining wider application in semiconductor process because it offers significant advantages over conventional process of etching metals. For example, it does not require etching of metals, such as copper and to a lesser degree, aluminum, which are more difficult to pattern and etch than dielectric materials. Additionally, the dual damascene process involves less process steps than conventional techniques that form vias as a separate step.
Unfortunately, the metal vias and trenches formed through the conventional dual damascene process typically suffer from adverse electromigration effects that often lead to device failure. By way of example, Prior Art FIG. 1 illustrates cross sectional view of a silicon wafer stack 100 formed using a conventional dual damascene process. The wafer stack 100 includes a substrate 102 and an oxide layer 104, a metallization layer 106, a barrier layer 110, an intermetal oxide (IMO) layer 108, and a pair of metal vias 118 and 120, and a metal interconnect line 112. The oxide layer 104 is formed over the substrate 102 and the metallization layer 106 is formed over the oxide layer 104. The barrier layer 110, the IMO layer 108, the metal interconnect line 112, and the metal vias 118 and 120 arc formed over portions of the oxide layer 104 and the metallization layer 106 using conventional dual damascene process.
In this wafer stack configuration, when an electric potential is applied across the metallization layer 106, the electric potential causes an eletromigration effect in the metal interconnect 116 and the metal vias 118 and 120. Specifically, the electric potential causes one metallization portion to be a cathode and the other metallization portion to be an anode. The electric potential between the cathode and anode causes a current flow from the anode end to the cathode end through the metal interconnect 112 and metal vias 118 and 120.
Since the direction of electrons is opposite of the direction of current flow, the electrons migrate from the cathode end of the metal via 120 toward the anode end of the metal via 118. In this process, the moving electrons generate an "electron wind," which pushes or forces the metal atoms in the direction of the electrons from the metal via 120 near the cathode toward the metal via 118 near the anode. The barrier layer 110 prevents the electrons and atoms in the metal vias 118 and 120 from migrating to and from the metal layer 106 underneath. As a result, a void 114 forms near the cathode in the metal via 120 while atoms accumulate as a hilllock 116 near the anode in the metal via 118. The void near the cathode in the metal via 120 often leads to device failure. Accordingly, voiding in a metal via undermines reliability of semiconductor devices produced by conventional dual damascene processes.
Furthermore, the voiding problem limits the current through the metal vias 118 and 120. This is because the size of the void increases as the current density through the metal vias 118 and 120 increases. Hence, to avoid voiding that may lead to an open circuit, the metal vias 118 and 120 may not be able to conduct a high current density.
In view of the foregoing, what is needed is a method for preventing voids in a metal via to ensure fabrication of more reliable semiconductor devices. In addition, what is needed is a method for reducing an electromigration effect through metal vias and trenches produced by a dual damascene process. What is also needed is a method of forming a metal via capable of conducting higher current densities.